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022CY7C10
PRELIMINARY
CY7C1022
32K x 16 Static RAM
Features
* 5.0V operation ( 10%) * High speed -- tAA = 12 ns * Low active power -- 825 mW (max., 10 ns, "L" version) * Very Low standby power -- 500 W (max., "L" version) * Automatic power-down when deselected * Independent Control of Upper and Lower bytes * Available in 400-mil SOJ enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable (CE) HIGH and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE HIGH, and WE LOW). The CY7C1022 is available in standard 400-mil-wide SOJ packages.
Functional Description
The CY7C1022 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking chip enable (CE) input HIGH and write enable (WE) input LOW. If byte low
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ Top View NC A 14 A 13 A 12 A11 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A10 A9 A8 A7 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A6 A5 A4 A3 A2 A1 A0
32K x 16 RAM Array
I/O1 - I/O8 I/O9 - I/O16
COLUMN DECODER BHE WE CE OE BLE
A0 A1 A2 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A3 A4 A5 A6 NC
ROW DECODER
A7 A8 A9 A10 A11 A12 A13 A14
SENSE AMPS
1022-2
2CY7C1022
Selection Guide
7C1022-12 Maximum Access Time (ns) Maximum Operating Current (mA) L Maximum CMOS Standby Current (mA) L
Shaded areas contain advance information.
7C1022-15 15 160 130 3 0.1
12 170 140 3 0.1
Cypress Semiconductor Corporation Document #: 38-05090 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 18, 2001
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................-65xC to +150xC Ambient Temperature with Power Applied............................................-55xC to +125xC Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V
CY7C1022
DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range Commercial Ambient Temperature[2] 0C to +70C VCC 4.5V-5.5V
Electrical Characteristics Over the Operating Range
7C1022-12 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs
[1]
7C1022-15 Min. 2.4 Max. 0.4 2.2 -0.5 -1 -2 6.0 0.8 +1 +2 160 130 20 10 3 0.1 mA mA mA Unit V V V V A A mA
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max. 0.4
2.2 -0.5 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 L -1 -2
6.0 0.8 +1 +2 170 140 20
ISB1
L
10 3
ISB2
L
0.1
Shaded area contains advance information.
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THEVENIN EQUIVALENT R2 255 R 481 R 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 167 30 pF R2 255 GND <3ns 3.0V 90% 10% 90% 10% <3ns ALL INPUT PULSES
(b)
1022-3 1022-4
1.73V
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05090 Rev. **
Page 2 of 8
PRELIMINARY
Switching Characteristics[4] Over the Operating Range
7C1022-12 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE HIGH to Low Z
[5, 6] [6]
CY7C1022
7C1022-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 7 0 7 15 10 10 0 0 10 10 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 9 ns ns
Description
Min. 12
Max.
12 3 12 6 0 6 3 6 0 12 6 0 6 12 9 8 0 0 8 6 0 3 6 8
CE LOW to High Z[5, 6] CE HIGH to Power-Up CE LOW to Power-Down Byte enable to Data Valid Byte enable to Low Z Byte disable to High Z
[7]
Write Cycle Time CE HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z
[6]
WE LOW to High Z[5, 6] Byte enable to end of write
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE HIGH, WE LOW and BHE / BLE LOW. CE HIGH, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05090 Rev. **
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PRELIMINARY
Switching Waveforms
Read Cycle No.1
[8, 9]
CY7C1022
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1022-5
Read Cycle No.2 (OE Controlled)
ADDRESS
[9, 10]
CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tPU 50%
tRC
tHZOE
tHZCE tHZBE DATA VALID tPD 50% IISB SB
1022-6
HIGH IMPEDANCE
DATA OUT
IICC CC
Notes: 8. Device is continuously selected. OE, CE, BHE and/or BHE = VIL 9. WE is HIGH for read cycle. 10. Address valid prior to or coincident with CE transition HIGH.
Document #: 38-05090 Rev. **
Page 4 of 8
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
[11, 12]
CY7C1022
tWC ADDRESS
tSA CE tAW
tSCE
tHA tPWE
WE tBW BHE, BLE tSD DATAI/O
1022-7
tHD
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATAI/O tHD
tHA
1022-8
Notes: 11. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 12. If CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05090 Rev. **
Page 5 of 8
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)
CY7C1022
tWC ADDRESS
tSCE CE tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
1022-10
Truth Table
CE L H OE X L WE X H BLE X L L H H X L L L H H H H X H X X H BHE X L H L L H L X H I/O1 - I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9 - I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 12 Ordering Code CY7C1022-12VC Package Name V34 Package Type 44-Lead (400-Mil) Molded SOJ Operating Range Commercial
Document #: 38-05090 Rev. **
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PRELIMINARY
Package Diagram
44-Lead (400-Mil) Molded SOJ V34
CY7C1022
Document #: 38-05090 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1022
Document Title: CY7C1022 32k x 16 Static RAM Data Sheet Document Number: 38-05090 REV. ** ECN NO. 110184 Issue Date 09/29/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00636 to 38-05090
Document #: 38-05090 Rev. **
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